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esmt preliminary EML3172 elite semiconductor memory technology inc. publication date : dec. 2013 revision : 0.1 1/17 3a, synchronous step-down dc-dc converter general description EML3172 is a high effici ency, dc-dc synchronous buck converter which provides 3a output loading after output voltage reach preset voltage. EML3172 uses different modulation algorithms for various loading conditions. under heavy load, EML3172 regulates the output voltage using pulse width modulation (pwm). the pwm mode provides low output voltage ripple and fixed frequency noise. while in light load, it enters power save modulation (psm) automatically to ensure a highly efficient operation at light load condition. under very heavy load condition or when the input voltage approaches the output voltage, EML3172 enters low dropout voltage operation under 100% duty cycle. the internal generated 0.8v precision feedback reference voltage is designed for low output voltage request. low power-fet ron synchronous switch dramatically reduces conduction loss. the EML3172 is available in the tiny package of tsot-23-6. features ? wide operating voltage ranges : 2.5v to 5.5v ? 3a output current ? high efficiency buck power converter ? auto-select psm/pwm ? ldo mode: duty cycle: 100% ? synchronous power switches rectification, no schottky diode required ? 1.4mhz switching frequency ? internal soft-start ? current limit protection ? over temperature protection ? output shorting protect ? output over voltage protection applications ? cellular telephone ? wireless and dsl modems ? digital still cameras ? portable products ? mp3 players typical application vin sw fb 43 6 cin* 22uf*2 v in cout* 22uf*2 v out EML3172 en 1 * ceramic capacitor 2.2uh r1 r2 gnd 2 ) 1 ( 2 1 r r v v fb out ? ? ? c fb * (option) fig. 1 EML3172 application circuit
esmt preliminary EML3172 elite semiconductor memory technology inc. publication date : dec. 2013 revision : 0.1 2/17 package configuration nc 5 tsot-23-6 fb 6 4 1 3 2 vin en gnd sw tsot-23-6 EML3172-xxvt06nrr --------------------------------------------------- xx output voltage 00 adjustable output --------------------------------------------------- vt06 tsot-23-6 package nrr rohs & halogen free package commercial grade temperature rating: -40 to 85c package in tape & reel order, mark & packing information package vout(v) product id marking packing tsot-23-6 adjustable EML3172-00vt06nrr 3172 tracking code 6 4 1 3 2 pin1 dot 5 tape & reel 3k units functional block diagram vin gnd control logic sw zcd current sense en fb ovp error amplifier modulator - + slope comp. osc soft start en ocp 0.8/vref otp comp fig. 2
esmt preliminary EML3172 elite semiconductor memory technology inc. publication date : dec. 2013 revision : 0.1 3/17 pin functions pin name tdfn-8l function en 1 enable pin. chip enable pin (1:enable ; 0:disable). gnd 2 power switch ground pin. sw 3 switch pin. must be connected to inductor. this pin connects to the drains of the internal main and synchronous power mosfet switches. vin 4 power supply pin. must be closely decoupled to gnd pin with 22 f*2 or greater ceramic capacitor. nc 5 no connect pin no internal connect. fb 6 feedback pin. receives the feedback voltage from an external resistive divider across the output.
esmt preliminary EML3172 elite semiconductor memory technology inc. publication date : dec. 2013 revision : 0.1 4/17 absolute maximum ratings devices are subjected to fail if they stay above absolute maximum ratings. input voltage (vin) ------------------------- ? 0.3v to 6.0v en, fb voltages -------------------------------- ? 0.3v to v in sw voltage -------------------------- ? 0.3v to (v in + 0.3v) lead temperature (soldering, 10 sec)----------- 260c operating temperature range ----- ?40c to 85c junction temperature (note 1) ------------------- 150c storage temperature range -------- ? 65c to 150c thermal data package thermal resistance parameter value ja (note 2) junction-ambient 110 o c/w tsot-23-6 jt (note 3) junction-top of package 8.5 o c/w electrical characteristics v in =v vcc =v en =3.6v, v out =1.2v, v fb =0.8v, l=2.2uh, c in =22uf*2, c out =22uf*2, t a = 25c, unless otherwise noted. symbol parameter conditions min typ max units v in input voltage range 2.5 5.5 v switching (en=vcc) 220 a i q supply current v in =3.6v shutdown (en=0) 1 a uvlo under voltage lockout when sw starts/stops switching 1.8 2.1 v vref reference voltage v in = 2.5v to 5.0v 0.784 0.8 0.816 v v en enable threshold -40 ~ +85 0.4 1.5 v vo output voltage range when using external feedback resistors to drive fb 0.8 vin v vout output voltage accuracy 2.5v Q v i Q 5.5v, 0ma Q i o Q 3a 0.97xv nom v nom 1.03xv nom v ? v out / ? v ou line regulation v out =1.2v, v in = 2.5v to 5.0v, i out =10ma 0.04 %/v ? v out / ? i out load regulation i out = 1ma to 3.0a 0.01 %/a r on(p) r ds(on) of pmos i out =100ma 60 m ? r on(n) r ds(on) of nmos i out =100ma 50 m ? i och high side current limt 3.75 4.5 6 a i ocl low side current limt duty cycle = 100%, v in = 2.5v to 5.0v -0.6 a f osc oscillator frequency vfb=0.8v, -40 ~+85 1.12 1.4 1.68 mhz max. duty maximum duty 100 % min. duty minimum duty. v in = 2.5v to 5.0v 15 % otp thermal shutdown hysteresis=35 165 note 1: t j is a function of the ambient temperature t a and power dissipation p d (t j = t a + (p d ) * ja )). note 2: ja is measured in the natural convection at t a =25 on a highly effective thermal conductivity test board(2 layers , 2s0p ) according to the jedec 51-7 thermal measurement standard. note 3: jt represents the heat resistance between the chip and the center of package top, that?s obtained by simulating a cold plate test on the top of the package.
esmt preliminary EML3172 elite semiconductor memory technology inc. publication date : dec. 2013 revision : 0.1 5/17 typical performance characteristics v in =5.0v, t a =25 , l=2.2uh, c in =22uf*2, c out =22uf*2, unless otherwise specified efficiency vs. load (fig. 3) efficiency vs. load (fig. 4) 0 10 20 30 40 50 60 70 80 90 100 1 10 100 1000 10000 output current (ma) efficiency(%) 0 10 20 30 40 50 60 70 80 90 100 1 10 100 1000 10000 output current (ma) efficiency (%) load regulation (fig. 5) load regulation (fig. 6) 3.24 3.26 3.28 3.30 3.32 3.34 3.36 1 10 100 1000 10000 output current (ma) output voltage(v) 1.14 1.16 1.18 1.20 1.22 1.24 1 10 100 1000 10000 output current (m a) out p ut volat g e ( v ) quiescent current vs. input voltage (fig. 7) quiescent current vs. temperature (fig. 8) 0 50 100 150 200 250 300 2.5 3.0 3.5 4.0 4.5 5.0 5.5 input voltage (v) quiescent current (ua ) 0 50 100 150 200 250 300 -40 -20 0 20 40 60 80 100 120 140 temperature ( ) quiescent c urrent (ua) v i =5.0v v i =4.2v v i =2.5v v 0 =1.2v v i =4.2v v o =3.3v v i =3.6v v i =5.0v v i =5.0v v i =5.5v v o =3.3v v i =5.5v v i =5.0v v o =1.2v t=25 v fb = 0. 9 v v i =5.0v v fb = 0. 9 v quiescent current quiescent current
esmt preliminary EML3172 elite semiconductor memory technology inc. publication date : dec. 2013 revision : 0.1 6/17 typical performance characteristics v in =5.0v, t a =25 , l=2.2uh, c in =22uf*2, c out =22uf*2, unless otherwise specified start-up, enable from en pin (fig. 9) short circuit response (fig. 10) psm operation (fig. 11) pwm operation (fig. 12) load transient response (fig. 13) load transient response (fig. 14) enable input output voltage sw voltage v i =5.0v v o =3.3v i o =10ma output voltage sw voltage inductor current v i =5.0v output voltage (3.3v dc offset) sw voltage inductor current v i =5.0v v o =3.3v i o =10ma output voltage (3.3v dc offset) sw voltage inductor current v i =5.0v v o =3.3v i o =500ma output current (500ma to 3a load step) output voltage (3.3v dc offset) v i =5.0v, v o =3.3v t r =12.2us, t f =12.8us c o =22uf*2, l=2.2uh output voltage (3.3v dc offset) output current (10ma to 3a load step) v i =5.0v, v o =3.3v t r =14.8us, t f =15.2us c o =22uf*2, l=2.2uh
esmt preliminary EML3172 elite semiconductor memory technology inc. publication date : dec. 2013 revision : 0.1 7/17 typical performance characteristics v in =5.0v, t a =25 , l=2.2uh, c in =22uf*2, c out =22uf*2, unless otherwise specified output voltage vs. temperature (fig. 15) os cillator frequency vs. temperature (fig.16) 3.24 3.26 3.28 3.30 3.32 3.34 3.36 -40 -15 10 35 60 85 temperature ( ) out p ut volta g e ( v ) 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 -40 -15 10 35 60 85 temperature (c) fre q uenc y ( mhz ) psm/pwm boundaries (fig.17) psm/pwm boundaries (fig.18) 0 10 20 30 40 50 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5 input voltage (v) output current (ma) 0 100 200 300 400 500 600 700 2.5 3.0 3.5 4.0 4.5 5.0 5.5 input voltage (v) output voltage (ma) output voltage ripple (fig.19) output voltage ripple (fig.20) 0 10 20 30 40 50 60 70 80 90 100 110 120 0 100 200 300 400 500 600 output current (ma) out p ut volta g e ri pp le ( mv ) 0 10 20 30 40 50 60 70 80 90 100 0 5 10 15 20 25 30 35 40 45 50 output current (ma) o u tp u t v o lta g e r ip p le (m v ) v i =5.0v v o =3.3v i o =500ma output voltage v i =5.0v v o =3.3v i o =500ma oscillator frequency always pwm always psm the switching mode changes at these boundaries. v o =3.3v c o =22uf*2 l = 2.2uh v o =1.2v c o =22uf*2 l = 2.2uh v o =1.2v c o =22uf*2 l = 2.2uh v o =3.3v c o =22uf*2 l = 2.2uh always psm always pwm the switching mode changes at these boundaries. v i = 5.0 v v i = 4.2 v v i = 3. 6v v i = 5.0 v v i = 5.5 v v i = 4.2 v
esmt preliminary EML3172 elite semiconductor memory technology inc. publication date : dec. 2013 revision : 0.1 8/17 application information detailed description the EML3172 is a synchronous, step-down dc/dc converter. it allows up to 3a current output with adjustable output voltage. throughout the entire operating range, EML3172 can maintain high efficiency using both pwm (heavy load) and psm (light load) modes with ve ry small output voltage ripple performance. during normal operation, the internal oscillator sends a pulse signal to set latch to turn on/off internal high-side mosfet and low-side mosfet during each clock cycle. when the current-mode ramp signal which is the sum of internal high-side mosfet current and slope compensa tion ramp exceeds output vo ltage of error amplifier, the pwm comparator will send a signal to reset latch and turn off/on internal high-side mosfet/low-side mosfet. the error amplifier adjusts its output voltag e by comparing the reference voltage and the feedback voltage. the basic EML3172 application circuits are shown as in figure 1, external components selection is determined by the load current and is critical with the selection of inductor and capacitor values. psm in order to increase light load efficiency, save switchin g loss is used in EML3172. during in light load, the device only switching when output voltage is below the pre-set threshold. this function can skip some switching cycle that save unnecessary loss. the fig.11 illustrates, as th e loading increases, the operation frequency increases until ic goes into normal operation frequency 1.4mhz . the fig.11 and fig.12 illustrate the difference between psm and pwm output voltage ripple. the switching freque ncy and output ripple is dependant on factors such as loading, inductor and output capacitance. besides, the input and output voltage ratio is a factor which affects device going psm mode or not. reference fig. 17, as input voltage decreases, psm/pwm boundary decreases to close 0ma. keep light load in psm, v in > v out +1v is necessary. inductor selection the value of the inductor is selected based on the desired ripple current. large inductance gives low inductor ripple current and small inductance result in high ripple current. however, the larger value inductor has a larger physical size, higher series resistance, and/or lower saturation current. in experience, the value is to allow the peak-to-peak ripple current in the inductor to be 10 %~20% maximum load current. the inductance value can be calculated by: ?? ?? in out load osc out in in out l osc out in v v * i * %) ~ % ( * * f ) v v ( v v * i * f v v l 20 10 2 ? ? ? ? the inductor ripple current can be calculated by: ? ? ? ? ? ? ? ? ? ? in out osc out l v v * l * f v i 1
esmt preliminary EML3172 elite semiconductor memory technology inc. publication date : dec. 2013 revision : 0.1 9/17 choose an inductor that does not saturate under the worst-case load conditions, which is the load current plus half the peak-to-peak inductor ripple current, even at the highest operating temperature. the peak inductor current is: 2 _ l load peak l i i i ? ? ? the inductors in different shape and style are available from manufacturer s. shielded inductors are small and radiate less emi issue. but they cost more than unshield ed inductors. the choice depends on emi requirement, price and size. recommend table inductor value (h) dimensions (mm) component supplier model isat (a) dcr (m ) 2.2 5.2 x 4.9 x 3.0 max. cyntec pcmb053t-2r2ms 9 29 typ. 2.2 4.9 x 4.9 x 4.1 ty p. taiyo yuden nrs5040t2r2nmgj 5 28.6 typ. input capacitor selection the input capacitor must be connected to the vin pi n and gnd pin of EML3172 to maintain steady input voltage and filter out the pulsing inpu t current. the voltage rating of input capacitor must be greater than maximum input voltage plus ripple voltage. in normal operation, the input current is discontinuous in a buck converter. the source current waveform of the high-si de mosfet is a square wave. to prevent large voltage transients, a low esr input capacitor sized for the maxi mum rms current must be used. the rms value of input capacitor current can be calculated by: ? ? ? ? ? ? ? ? ? ? in out in out max _ load rms v v * v v * i i 1 it can be seen that when v o is half of v in , c in is under the worst current stress . the worst current stress on c in is i o_max /2. a 22 f*2ea ceramic capacitor is recommended value in typical application. output capacitor selection the output capacitor is required to maintain the dc ou tput voltage. low esr capacitors are preferred to keep the output voltage ripple low. in a buck converter circuit, output ripple voltage is determined by inductor value, switching frequency, output capacitor value an d esr. the output ripple is determined by: ? ? ? ? ? ? ? ? ? ? out osc cout l out c * f * esr * i v 8 1
esmt preliminary EML3172 elite semiconductor memory technology inc. publication date : dec. 2013 revision : 0.1 10/17 where f osc = operating frequency, c out = output capacitance and i l = ripple current in the inductor. for a fixed output voltage, the output ripple is highest at maximum input voltage since i l increases with input voltage. a 22 f ceramic capacitor is recommended value in typical application. recommend table capacitor value (f) case size component supplier model 22 0805 1206 tdk c3216x5r1e226k using ceramic input and output capacitors care must be taken when ceramic capacitors are used at the input and the output. when a ceramic capacitor is used at the input and the power is supplied by a wall adapter through long wires, a load step at the output can induce ringing at the input, vin. at best, this ringing can couple to the output and be mistaken as loop instability. at worst, a sudden inrush current through the long wires can potentially cause a voltage spike at v in , which may large enough to damage the part . when choosing the inpu t and output ceramic capacitors, choose the x5r or x7r specification. thei r dielectrics have the best temperature and voltage characteristics of all the ceramics for a given value and size. load transient a switching regulator typically takes several cycles to respond to the load current step. when a load step occurs, vout immediately shifts by an amount equal to cout load esr * i esr is the effective series resistance of output capacitor. i load also begins to charge or discharge c out generating a feedback error signal used by the regulator to return v out to its steady-state value. during the recovery time, v out can be monitored for overshoot or ringing that would indicate a stability problem. short-circuit protection when EML3172 output node is shorted to gnd, chip will en ter soft-start to protect itself, when short circuit is removed, EML3172 enter normal operation again. if EML3172 reach ocp threshold while short circuit, EML3172 will enter soft-start cycle until the current under ocp threshold. over temperature protection the internal high-side mosfet is turned off when the internal thermal sensor detects that the junction temperature exceeds 165 , entering the over temperature protection mode (otp). the otp mode is unlocked at 130 , i.e. 35 hysteresis.
esmt preliminary EML3172 elite semiconductor memory technology inc. publication date : dec. 2013 revision : 0.1 11/17 output voltage setting the output voltage of EML3172 can be adjusted by a re sistive divider according to the following formula: ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 2 1 2 1 1 * 8 . 0 1 * r r r r v v ref out the resistive divider senses the fraction of the output voltage as shown in fig.21 using large feedback resistor can increase efficiency, but too large value affects the device?s output accuracy because of leakage current going into device?s fb pin. the recommended va lue for r2 is therefore in the range of 50k ? . fb gnd v out r1 EML3172 r2 fig. 21 setting the output voltage under voltage lock out the under-voltage lockout (uvlo) circuitry ensures that the EML3172 starts up with adequate voltage. the regulator output is disabled whenever vin is below uvlo . the hysteresis of uvlo is designed to be 100 mv.
esmt preliminary EML3172 elite semiconductor memory technology inc. publication date : dec. 2013 revision : 0.1 12/17 application circuits information ? application circuit for maximum 2a load vin sw fb 43 6 cin* 22uf*1 v in cout* 22uf*1 EML3172 en 1 * ceramic capacitor 2.2uh r1 r2 gnd 2 ) 1 ( 2 1 r r v v fb out ? ? ? c fb * (option) note. it?s recommended that c in =22 f x 2ea for short protection circuit work sell considering at low temperature lower than -20 . ? application circuit for maximum 3a load vin sw fb 43 6 cin* 22uf*2 v in cout* 22uf*1 v out EML3172 en 1 * ceramic capacitor 2.2uh r1 r2 gnd 2 ) 1 ( 2 1 r r v v fb out ? ? ? c fb * (option) note. it?s recommended that c out =22uf x 2ea for load regulation considering application.
esmt preliminary EML3172 elite semiconductor memory technology inc. publication date : dec. 2013 revision : 0.1 13/17 applications typical schematic for pcb layout 1 1 2 2 3 3 j1 en + c1 + c2 + c3 + c4 l1 r1 r2 r3 gnd gnd fb en en sc sc1 fvin sc sc2 svin sc sc3 fvout sc sc4 svout sc sc5 fgnd sc sc6 sgnd sc sc7 sw sc sc8 vfb vin vin vin vin fb fb vout vout vout gnd gnd gnd sw sw en 1 gnd 2 sw 3 vin 4 nc 5 fb 6 u1 EML3172 fig. 22 pcb layout guidelines when laying out the printed circuit board, the following checklist should be used to optimize the performance of EML3172. 1. the power traces, including the gnd trace, the sw trace and the in v trace should be kept direct, short and wide. 2. put input capacitor as close as possible to the v in and gnd pins. 3. the fb pin should be connected directly to the feedback resistor divider. 4. keep the switching node, sw, away from the sensit ive fb pin and the node should be kept small area.
esmt preliminary EML3172 elite semiconductor memory technology inc. publication date : dec. 2013 revision : 0.1 14/17 typical schematic for pcb layout (cont.) top layer bottom layer
esmt preliminary EML3172 elite semiconductor memory technology inc. publication date : dec. 2013 revision : 0.1 15/17 package outline drawing tsot-23-6 l a a1 e b d ee1 c 123 4 5 6 123 top view detail a side view detail a min. max. a 0.90 1.45 a1 0.00 0.15 b 0.30 0.50 c 0.08 0.25 d 2.70 3.10 e 1.40 1.80 e1 2.60 3.00 e l 0.30 0.60 0.95 bsc symbol dimension in mm
esmt preliminary EML3172 elite semiconductor memory technology inc. publication date : dec. 2013 revision : 0.1 16/17 revision history revision date description 0.1 2013.12.27 draft version.
esmt preliminary EML3172 elite semiconductor memory technology inc. publication date : dec. 2013 revision : 0.1 17/17 important notice all rights reserved. no part of this document may be repr oduced or duplicated in any form or by any means without the prior permission of esmt. the contents contained in this docume nt are believed to be accurate at the time of publication. esmt assumes no responsibility for any error in this document, and reserves the right to change the products or specification in this document without notice. the information contained herein is pr esented only as a guide or examples for the application of our products. no responsibility is assumed by esmt for any infringement of patents, copyrights, or other intellect ual property rights of third parties which may result from its use. no license, either express, implied or otherwise, is granted un der any patents, copyrights or other intellectual property righ ts of esmt or others. any semiconductor devices may have in herently a certain rate of failure. to minimize risks associated with cu stomer's application, adequate design and operating safeguards against inju ry, damage, or loss from such failure, should be provided by the customer when making application designs. esmt's products are not authorized for use in critical applications such as, but not limited to, life support devices or system, where failure or abnormal operation may directly affect human lives or cause physical injury or property damage. if products described here are to be used for such kinds of application, purchaser must do its own quality assurance testing appropriate to such applications.

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